SUTD researchers are developing a new reconfiguration

Picture 1

image: Schematic representation of loading data into the device and retrieving from it that takes place in the serial model, i.e. parallel mode of operation (left panel) and a table showing state changes in three bits during operations (right panel).
view more

Credits: SUTD

The development of energy-efficient high-performance computing devices, i.e. devices that not only consume little energy, but also calculate information quickly, is a key goal of edge computing research. A combination of memory components and units that perform shift register operations is a potential way to achieve this goal.

Most computing devices consist of a physically separate memory component and processing unit. However, in order to greatly simplify these devices and reduce their power consumption, a device has been developed that can potentially perform both functions effectively – the memory shift register architecture.

Conventional in-memory shift register architectures have limitations, although some of these architectures show promising results. Limitations include the use of many devices and the requirement to convert electrical resistance into electrical signals.

Based on phase change alloys, materials that reversibly switch between a glassy amorphous state and an ordered crystalline state, researchers at the Singapore University of Technology and Design (SUTD) have developed a new reconfigurable memory shift register architecture. Their device works as both a reconfigurable memory component and a programmable shift register, and is presented in a paper published in Advanced intelligent systems.

The term “material state-based shift register” has been used to describe the in-memory shift register device developed by the researchers. Four material states were used for device operation, i.e., amorphous state, fully crystalline state, partially crystallized state, and initial phase change material state (representing different shift register/memory modes).

The device can be switched to perform either shift register or memory functions and is easy to program thanks to its special design. The researchers showed in preliminary tests that the device had impressive results for both functions.

“When operating as a memory, the device can be switched from the disordered glass state to the crystalline state with 1.9 ns pulses, which is about one-third shorter than that of existing devices with nitrogen-doped germanium antimony telluride layers; and exhibit a reset energy of 2 pJ. When operating as a shift register, the device can switch between serial-in-serial-out mode and serial-in-parallel-out mode, with a single cell, and exhibit many levels of resistance, which has not been shown before,” said SUTD – Assistant Professor Desmond Loke, who is the principal investigator of the study.

To significantly reduce power consumption, the new memory shift register architecture proposed by the research team could be used to design a wide range of high-performance electronic systems in the future. M state-based shift registers can be applied to a variety of operational schemes and calculations, although for the purposes of this study the researchers demonstrated that these devices can successfully perform shift register operations.

Other researchers involved in this work were Shao-Xiang Go, Qiang Wang, Nataša Bajalović from SUTD, Taehoon Lee from Cambridge University and Kejie Huang from Zhejiang University.

Waiver: AAAS and EurekAlert! are not responsible for the accuracy of press releases published on EurekAlert! by the contributing institutions or for the use of any information through the EurekAlert system.

Leave a Comment

Your email address will not be published. Required fields are marked *